Method of accessing data of a computer system

ABSTRACT

A method for accessing data in a computer system. The computer system has a first memory, a second memory, an address decoder, a digital signal processing cell, a demultiplexer, a multiplexer, and a cache memory. The cache memory includes a tag for storing an address. The method includes controlling the demultiplexer with the address decoder according to an address signal generated by the digital signal processing cell to transmit the address signal either to the cache memory or to the second memory via the demultiplexer, and controlling the multiplexer with the address decoder according to the address signal to control the digital signal processing cell to receive data transmitted either from the cache memory or from the second memory via the multiplexer.

BACKGROUND OF INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a computer system, and moreparticularly, to a method of accessing data of the computer system witha digital signal processing chip having a static random access memory(SRAM) and a cache memory.

[0003] 2. Description of the Prior Art

[0004] The dramatic development of communications technologies demandshigh-efficiency digital signal processing (DSP) chips. A DSP chip iscapable of executing a plurality of operations in a single instructioncycle and can substitute for a central processing unit (CPU) to executecomplex arithmetic operations, such as convolution and fast Fouriertransform (FFT), so that the CPU can concentrate on system control.

[0005] Please refer to FIG. 1, which is a function block diagram of acomputer system 10 according to the prior art. The computer system 10comprises a DSP chip 12 and a dynamic random access memory (DRAM) 14electrically connected to the DSP chip 12 via a plurality of addresslines 16 and data lines 18. The DSP chip 12 is capable of accessing andprocessing data of the DRAM 14 through the address lines 16 and datalines 18. In general, time for the DSP chip 12 to access data of theDRAM 14 through the address lines 16 and data lines 18 is approximatelysix times longer than time needed to process these accessed data (clockcycle). For example, if the DSP chip 12 has a clock cycle rangingbetween 120 MHz to 250 MHz, time for the DSP chip 12 to access one setof data is around 48-24 nanoseconds, which is far longer than 4-8nanoseconds, time for the DSP chip 12 to process these data. Inconclusion, how fast the DSP chip 12 accesses data of the DRAM 14dominates the efficiency of the DSP chip 12.

[0006] A concept of embedding an embedded memory is introduced toimprove the efficiency of the DSP chip 12. Please refer to FIG. 2, whichis a function block diagram of another computer system 20 according tothe prior art. The computer system 20 comprises a DSP chip 22 and a DRAM24 electrically connected to the DSP chip 22 via a plurality of addresslines 26 and data lines 28. The DSP chip 22 comprises a static randomaccess memory (SRAM) 30. Because time for the DSP chip 22 to access oneset of data of the SRAM 30 is around only 3 nanoseconds, far shorterthan 48-24 nanoseconds, data frequently used by the DSP chip 22 can bestored in the SRAM 30 in advance to improve the efficiency of thecomputer system 30.

[0007] However, the DSP chip 22 with the SRAM 30 embedded still has someshortcomings. For example, if a working space for the DSP chip 22 tostore the frequent-used data is 12K words large, the SRAM 30 embeddedinto the DSP chip 22 also has to have a corresponding storing space of12K words reserved. In general, a program code the DSP chip 22 manageshas a size of 4K words for example, smaller than 12K words, so the SRAM30 has two thirds of its storing space idled. This idle storing space ofthe SRAM 30 not only increase cost to produce the DSP chip 22, since theSRAM 30 occupies major area of the DSP chip 22, the idle storing spacealso increases the bulk of the DSP chip 22.

[0008] In addition, the SRAM 30 having a constant storing space (forexample 12K words) limits the DSP chip 22 to execute an applicationprogram demanding a memory space less than 12K words.

[0009] Lastly, because a direct memory access (DMA) controller has to beintroduced to manage data communications between the SRAM 30 of the DSPchip 22 and the DRAM 24, a control program code stored in the DSP chip22 to control the DMA controller has to be changed accordingly if dataallocation of the SRAM 30 has changed.

SUMMARY OF INVENTION

[0010] It is therefore a primary objective of the claimed invention toprovide a method of accessing data of a computer with a DSP chip havingan embedded cache memory and an SRAM.

[0011] According to the claimed invention, the method is proposed foraccessing data of a computer system. The computer system has a firstmemory, a second memory, an address decoder, a digital signal processingunit electrically connected to the address decoder, a demultiplexerhaving an input end electrically connected to the digital signalprocessing unit, a first output end electrically connected to the secondmemory, and a control end electrically connected to the address decoder,and a multiplexer having an output end electrically connected to thedigital signal processing unit, a first input end electrically connectedto the second memory, and a control end electrically connected to theaddress decoder. The method has following steps: (a) providing thedigital signal processing unit with a cache memory electricallyconnected to the first memory, the cache memory having an input endelectrically connected to a second output end of the demultiplexer, anoutput end electrically connected to a second input end of themultiplexer, and a tag stored with an address data; and (b) when thedigital signal processing unit generates an address signal, (c)controlling the demultiplexer with the address decoder according to theaddress signal to transfer the address signal either to the cache memoryor to the second memory and to enable the digital signal processing unitto receive contents via the multiplexer either from the cache memory orfrom the second memory, (d) comparing the address signal with theaddress data if the address signal is transmitted to the cache memory,and either transmitting contents of the cache memory corresponding tothe address signal via the multiplexer to the digital signal processingunit if the address signal matches the address data or updating contentsof the cache memory corresponding to the address signal with contents ofthe first memory corresponding to the address signal, (e) updating theaddress data with the address signal and transmitting the updatedcontents of the cache memory via the multiplexer to the digital signalprocessing unit, and (f) transmitting contents of the second memorycorresponding to the address signal via the multiplexer to the digitalsignal processing unit if the address signal is transmitted to thesecond memory.

[0012] The address decoder, the second memory, the digital signalprocessing unit, the demultiplexer, the multiplexer, and the cachememory are all integrated into a single digital signal processing chip.

[0013] In the preferred embodiment, the first memory is a DRAM and thesecond memory is an SRAM.

[0014] It is an advantage of the claimed invention that a digital signalprocessing chip has not only an SRAM but also a cache memory embeddedand is capable of storing frequently-used data into the cache memory toimprove the efficiency of a computer which the digital signal processingchip is installed in.

[0015] These and other objectives of the claimed invention will no doubtbecome obvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF DRAWINGS

[0016]FIG. 1 is a function block diagram of a computer system accordingto the prior art.

[0017]FIG. 2 is a function block diagram of another computer systemaccording to the prior art.

[0018]FIG. 3 is a function block diagram of a computer system of apreferred embodiment according to the present invention.

[0019]FIG. 4 is a flow chart of a method of accessing data of thecomputer shown in FIG. 3 according to the present invention.

DETAILED DESCRIPTION

[0020] Please refer to FIG. 3, which is a function block diagram of acomputer system 40 of the preferred embodiment according of the presentinvention. The computer system 40 comprises a DSP chip 42 and a DRAM 44electrically connected to the DSP chip 42 via a plurality of addresslines 46 and data lines 48. The DSP chip 42 comprises an SRAM 50, anaddress decoder 52, a digital signal process unit 54 electricallyconnected to the address decoder 52, a delmultiplexer 56, a multiplexer58, and a cache memory 60 having a tag (not shown) for storing addressinformation. The demultiplexer 56 comprises an input end I electricallyconnected to the digital signal processing unit 54, a first output endO₁ electrically connected to the SRAM 50, and a control end D_(c)electrically connected to the address decoder 52. The multiplexer 58comprises an output end O electrically connected to the digital signalprocessing unit 54, a first input end I₁ electrically connected to theSRAM 50, and a control end D_(c) electrically connected to the addressdecoder 52. The cache memory 60 comprises an input end electricallyconnected to a second output end O₂ of the delmultiplexer 56, and anoutput end electrically connected to a second input end I₂ of themultiplexer 58.

[0021] Since time for the digital signal processing unit 54 to accessone set of data of the cache memory 60 is only 4 nanoseconds, farshorter than 42 nanoseconds, time for the digital signal processing unit54 to access one set of data of the DRAM 44, the DSP chip 40 can promotethe efficiency of the computer system 40 by selectively storingfrequently-used data and program codes to the cache memory 60.

[0022] In the preferred embodiment of the present invention, the SRAM 50has a memory space of 4K, and the cache memory 60 has a memory space of4K as well. Of course, the SRAM 50 as well as the cache memory 60 canhave memory space of a variety of sizes in accordance with practicaldemands.

[0023] Address lines 46 and data lines 48 installed in the DSP chip 42,for example address lines connecting the digital signal processing unit54 and the demultiplexer 56 and data lines connecting the multiplexer 58and the cache memory 60 or the SRAM 50, have a Harvard structure.Because time for address calculation is usually no less than that fordata calculation in the DSP chip 42, the DSP chip 42 of the Harvardstructure can further comprise an address generator (not shown) toaccelerate the address calculation.

[0024] A method 100 for the DSP chip 42 of the computer system 40 toprocess data or to execute program codes is described as follows: Pleaserefer to FIG. 4, which is a flow chart of the method 100 of accessingdata of the computer system 40 according to the present invention. Themethod 100 comprises following steps:

[0025] Step 101: Start;

[0026] Step 102: Generate a control signal to control the demultiplexer56 and the multiplexer 58 according to an address signal with theaddress decoder 52 when the digital signal processing unit 54 outputsthe address signal;

[0027] Step 104: Determine whether or not the address signal correspondsto the SRAM 50, if yes, go to step 120, else, go to step 140;

[0028] Step 120: Control the demultiplexer 56 to transfer the addresssignal via the demultiplexer 56 to the SRAM 50 and control themultiplexer 58 to enable the digital signal processing unit 54 toreceive data transferred from the SRAM 50 via the multiplexer 58;

[0029] Step 122: Transfer data of the SRAM 50 corresponding to theaddress signal via the multiplexer 58 to the digital signal processingunit 54, go to step 198;

[0030] Step 140: Control the demultiplexer 56 to transfer the addresssignal via the demultiplexer 56 to the cache memory 60 and control themultiplexer 58 to enable the digital signal processing unit 54 toreceive data transferred from the cache memory 60 via the multiplexer58;

[0031] Step 142: Compare the address signal with the addressin-formation stored in the tag of the cache memory 60;

[0032] Step 144: If the address signal hits the address information,then go to step 160, else (misses) go to step 180;

[0033] Step 160: Transfer data of the cache memory 60 corresponding tothe address signal via the multiplexer 58 to the digital signalprocessing unit 54, go to step 198;

[0034] Step 180: Update data of the cache memory 60 corresponding to theaddress signal with data of the DRAM 44 corresponding to the addresssignal;

[0035] Step 182: Update the address information of the tag of the cachememory 60 with the address signal:

[0036] Step 184: Transfer the updated data of the cache memory 60corresponding to the address signal via the multiplexer 58 to thedigital signal processing unit 54; and

[0037] Step 198: Ends.

[0038] In step 180, the address signal the DSP chip 42 generates can beused to address to a plurality of memory spaces of the DRAM 44 dependingon a setting between the DSP chip 42 and the cache memory. The addresssignal is a logical address corresponding to a physical address of theDRAM 44, the physical address equal to a sum of the logical address anda configurable base address stored in the cache memory 60. These arewell known in the prior art, and further description is hereby omitted.

[0039] In contrast to the prior art, the present invention can provide acomputer system 40, in which a DSP chip 42 comprises not only an SRAMbut also a cache memory. Therefore, as mentioned above, the computersystem 40 has advantages of small bulk, low cost, high efficiency, andremarkable expandability. In addition, with slight adjustment of thebase address, the DSP chip 42 can further access data stored in anothermemory space other than the DRAM 44 with the cache memory 60.

[0040] Following the detailed description of the present inventionabove, those skilled in the art will readily observe that numerousmodifications and alterations of the device may be made while retainingthe teachings of the invention. Accordingly, the above disclosure shouldbe construed as limited only by the metes and bounds of the appendedclaims.

What is claimed is:
 1. A method for accessing data of a computer system,the computer system comprising: a first memory; a second memory; anaddress decoder; a digital signal processing unit electrically connectedto the address decoder; a demultiplexer having an input end electricallyconnected to the digital signal processing unit, a first output endelectrically connected to the second memory, and a control endelectrically connected to the address decoder; and a multiplexer havingan output end electrically connected to the digital signal processingunit, a first input end electrically connected to the second memory, anda control end electrically connected to the address decoder; and themethod comprising following steps: (a) providing the digital signalprocessing unit with a cache memory electrically connected to the firstmemory, the cache memory having an input end electrically connected to asecond output end of the demultiplexer, an output end electricallyconnected to a second input end of the multiplexer, and a tag storedwith an address data; and (b) when the digital signal processing unitgenerates an address signal, (c) controlling the demultiplexer with theaddress decoder according to the address signal to transfer the addresssignal either to the cache memory or to the second memory and to enablethe digital signal processing unit to receive contents via themultiplexer either from the cache memory or from the second memory, (d)comparing the address signal with the address data if the address signalis transmitted to the cache memory, and either transmitting contents ofthe cache memory corresponding to the address signal via the multiplexerto the digital signal processing unit if the address signal matches theaddress data or updating contents of the cache memory corresponding tothe address signal with contents of the first memory corresponding tothe address signal, (e) updating the address data with the addresssignal and transmitting the updated contents of the cache memory via themultiplexer to the digital signal processing unit, and (f) transmittingcontents of the second memory corresponding to the address signal viathe multiplexer to the digital signal processing unit if the addresssignal is transmitted to the second memory.
 2. The method of claim 1wherein the address decoder, the second memory, the digital signalprocessing unit, the demultiplexer, the multiplexer, and the cachememory are all integrated into a digital signal processing chip.
 3. Themethod of claim 1 wherein the first memory is a dynamic random accessmemory (DRAM).
 4. The method of claim 1 wherein the second memory is astatic random access memory (SRAM).
 5. A computer system comprising: afirst memory; a second memory; an address decoder; a digital signalprocessing unit electrically connected to the address decoder; ademultiplexer having an input end electrically connected to the digitalsignal processing unit, a first output end electrically connected to thesecond memory, and a control end electrically connected to the addressdecoder; a multiplexer having an output end electrically connected tothe digital signal processing unit, a first input end electricallyconnected to the second memory, and a control end electrically connectedto the address decoder; and a cache memory having an input endelectrically connected to a second output end of the demultiplexer, anoutput end electrically connected to a second input end of themultiplexer, and a tag for storing an address.
 6. The computer system ofclaim 5 wherein the address decoder, the second memory, the digitalsignal processing unit, the demultiplexer, the multiplexer, and thecache memory are all integrated into a digital signal processing chip.7. The computer system of claim 5 wherein the first memory is a DRAM. 8.The computer system of claim 5 wherein the second memory is an SRAM.